A Security Verification Template to Assess Cache Architecture Vulnerabilities

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  • Additional Information
    • Publication Information:
      IEEE
    • Publication Date:
      2020
    • Abstract:
      In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.
    • Contents Note:
      Conference Acronym: DDECS
    • Author Affiliations:
      Tallinn University of Technology
      Delft Univeristy of Technology
    • ISBN:
      978-1-7281-9938-2
      978-1-7281-9937-5
    • ISSN:
      2473-2117
    • Relation:
      2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
    • Accession Number:
      10.1109/DDECS50862.2020.9095707
    • Rights:
      Copyright 2020, IEEE
    • AMSID:
      9095707
    • Conference Acronym:
      DDECS
    • Date of Current Version:
      2020
    • Document Subtype:
      IEEE Conference
    • Notes:
      Conference Location: Novi Sad, Serbia, Serbia

      Conference Start Date: 22 April 2020

      Conference End Date: 24 April 2020
    • Accession Number:
      edseee.9095707
  • Citations
    • ABNT:
      GHASEMPOURI, T. et al. A Security Verification Template to Assess Cache Architecture Vulnerabilities. 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium on, [s. l.], p. 1–6, 2020. DOI 10.1109/DDECS50862.2020.9095707. Disponível em: http://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.9095707. Acesso em: 1 dez. 2020.
    • AMA:
      Ghasempouri T, Raik J, Paul K, Reinbrecht C, Hamdioui S, Taouil M. A Security Verification Template to Assess Cache Architecture Vulnerabilities. 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium on. April 2020:1-6. doi:10.1109/DDECS50862.2020.9095707
    • APA:
      Ghasempouri, T., Raik, J., Paul, K., Reinbrecht, C., Hamdioui, S., & Taouil, M. (2020). A Security Verification Template to Assess Cache Architecture Vulnerabilities. 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium On, 1–6. https://doi.org/10.1109/DDECS50862.2020.9095707
    • Chicago/Turabian: Author-Date:
      Ghasempouri, Tara, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, and Mottaqiallah Taouil. 2020. “A Security Verification Template to Assess Cache Architecture Vulnerabilities.” 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium On, April, 1–6. doi:10.1109/DDECS50862.2020.9095707.
    • Harvard:
      Ghasempouri, T. et al. (2020) ‘A Security Verification Template to Assess Cache Architecture Vulnerabilities’, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium on, pp. 1–6. doi: 10.1109/DDECS50862.2020.9095707.
    • Harvard: Australian:
      Ghasempouri, T, Raik, J, Paul, K, Reinbrecht, C, Hamdioui, S & Taouil, M 2020, ‘A Security Verification Template to Assess Cache Architecture Vulnerabilities’, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium on, pp. 1–6, viewed 1 December 2020, .
    • MLA:
      Ghasempouri, Tara, et al. “A Security Verification Template to Assess Cache Architecture Vulnerabilities.” 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium On, Apr. 2020, pp. 1–6. EBSCOhost, doi:10.1109/DDECS50862.2020.9095707.
    • Chicago/Turabian: Humanities:
      Ghasempouri, Tara, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, and Mottaqiallah Taouil. “A Security Verification Template to Assess Cache Architecture Vulnerabilities.” 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium On, April 1, 2020, 1–6. doi:10.1109/DDECS50862.2020.9095707.
    • Vancouver/ICMJE:
      Ghasempouri T, Raik J, Paul K, Reinbrecht C, Hamdioui S, Taouil M. A Security Verification Template to Assess Cache Architecture Vulnerabilities. 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020 23rd International Symposium on [Internet]. 2020 Apr 1 [cited 2020 Dec 1];1–6. Available from: http://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.9095707