Single Ended Computational SRAM Bit-Cell

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  • Additional Information
    • Publication Information:
      IEEE
    • Publication Date:
      2019
    • Abstract:
      Dual port SRAM plays an important role in maintaining the bandwidth of dataflow between memory and processor. To improve data stability and bandwidth, the memory industry moved from conventional 6 transistor (6T) to 8 transistor (8T) SRAM but compromised on the layout area for additional stability. To address the trade-off between area and reliability, a novel Single Ended 8T SRAM is proposed in this paper along with its static analysis, transient response and power consumption, to observe its efficiency and reliability. The proposed SRAM bit-cell architecture is also capable of in-memory computation, thereby potentially avoiding the Von-Neumann bottleneck problem for some computations. In particular, the proposed SRAM can perform in-memory NAND and NOR operations, and may be useful for low-power and high-performance machine learning and neural network hardware architectures.
    • Contents Note:
      Conference Acronym: ISSCS
    • Author Affiliations:
      School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada
      Department of Electronics, Carleton University, Ottawa, Canada
    • ISBN:
      978-1-7281-3896-1
    • Relation:
      2019 International Symposium on Signals, Circuits and Systems (ISSCS)
    • Accession Number:
      10.1109/ISSCS.2019.8801735
    • Rights:
      Copyright 2019, IEEE
    • AMSID:
      8801735
    • Conference Acronym:
      ISSCS
    • Date of Current Version:
      2019
    • Document Subtype:
      IEEE Conference
    • Notes:
      Conference Location: Iasi, Romania, Romania

      Conference Start Date: 11 July 2019

      Conference End Date: 12 July 2019
    • Accession Number:
      edseee.8801735
  • Citations
    • ABNT:
      KAREER, S. et al. Single Ended Computational SRAM Bit-Cell. 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium on, [s. l.], p. 1–4, 2019. DOI 10.1109/ISSCS.2019.8801735. Disponível em: http://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.8801735. Acesso em: 31 out. 2020.
    • AMA:
      Kareer S, MacEachern L, Groza V, Park J. Single Ended Computational SRAM Bit-Cell. 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium on. July 2019:1-4. doi:10.1109/ISSCS.2019.8801735
    • APA:
      Kareer, S., MacEachern, L., Groza, V., & Park, J. (2019). Single Ended Computational SRAM Bit-Cell. 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium On, 1–4. https://doi.org/10.1109/ISSCS.2019.8801735
    • Chicago/Turabian: Author-Date:
      Kareer, Shobhit, Leonard MacEachern, Voicu Groza, and Jeongwon Park. 2019. “Single Ended Computational SRAM Bit-Cell.” 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium On, July, 1–4. doi:10.1109/ISSCS.2019.8801735.
    • Harvard:
      Kareer, S. et al. (2019) ‘Single Ended Computational SRAM Bit-Cell’, 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium on, pp. 1–4. doi: 10.1109/ISSCS.2019.8801735.
    • Harvard: Australian:
      Kareer, S, MacEachern, L, Groza, V & Park, J 2019, ‘Single Ended Computational SRAM Bit-Cell’, 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium on, pp. 1–4, viewed 31 October 2020, .
    • MLA:
      Kareer, Shobhit, et al. “Single Ended Computational SRAM Bit-Cell.” 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium On, July 2019, pp. 1–4. EBSCOhost, doi:10.1109/ISSCS.2019.8801735.
    • Chicago/Turabian: Humanities:
      Kareer, Shobhit, Leonard MacEachern, Voicu Groza, and Jeongwon Park. “Single Ended Computational SRAM Bit-Cell.” 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium On, July 1, 2019, 1–4. doi:10.1109/ISSCS.2019.8801735.
    • Vancouver/ICMJE:
      Kareer S, MacEachern L, Groza V, Park J. Single Ended Computational SRAM Bit-Cell. 2019 International Symposium on Signals, Circuits and Systems (ISSCS), Signals, Circuits and Systems (ISSCS), 2019 International Symposium on [Internet]. 2019 Jul 1 [cited 2020 Oct 31];1–4. Available from: http://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edseee&AN=edseee.8801735